DocumentCode
2261652
Title
Efficient template generation for instruction-based self-test of processor cores
Author
Kambe, Kazuko ; Inoue, Michiko ; Fujiwara, Hideo
Author_Institution
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science City, Japan
fYear
2004
fDate
15-17 Nov. 2004
Firstpage
152
Lastpage
157
Abstract
This paper presents a method of template generation for instruction-based self-test of processor cores. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and propagation of test responses for a module under test (MUT). In order to justify value of MUT inputs, we introduce a concept of adjacent registers of the MUT that makes it possible to consider input spaces of the MUT determined by signals from other modules as well as signals directly from registers. We efficiently generate possible templates considering dependence of instructions each of which invokes one or more data transfers between registers. The method also generates multiple templates in effective order to detect faults, which may cover different input spaces, and therefore, different detectable fault sets.
Keywords
automatic test pattern generation; built-in self test; circuit analysis computing; high-speed integrated circuits; integrated circuit testing; microprocessor chips; shift registers; adjacent registers; data transfers; detectable fault sets; fault detection; instruction-based self-test; module under test; processor cores; template generation; test patterns; test program template; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Microprocessors; Performance evaluation; Registers; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. 13th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2235-1
Type
conf
DOI
10.1109/ATS.2004.39
Filename
1376551
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