A systematic way of functional testing for VLSI chips

Author

Xu, Shiyi

Author_Institution

Shanghai Univ., China

fYear

2004

fDate

15-17 Nov. 2004

Firstpage

170

Lastpage

175

Abstract

In VLSI chips, the detail circuit implementation is always unknown; only the functional behavior could be known to the users. In this paper, we present a systematic technique for detecting and locating of both stuck-at and bridging faults on the primary input and output lines based on the functional behavior of the circuit being tested. The proposed technique could be quite helpful for both the academic and industrial users of VLSI chips for their testing of the stuck-at and bridging faults and verifying the functions before the chips are applied. Algorithms and experimental results of computer implementation of the scheme are reported.

Keywords

VLSI; circuit analysis computing; fault diagnosis; integrated circuit testing; logic testing; matrix algebra; VLSI chips; bridging faults; fault detection; fault location; fault testing; functional circuit behavior; functional testing; primary input line; primary output line; standard input matrix; stuck-at faults; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Feedback; Intellectual property; Manufacturing; Pins; System testing; Very large scale integration; Bridging fault; Functional behavior; Standard Input Matrix; Stuck-at-fault;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2004. 13th Asian

ISSN

1081-7735

Print_ISBN

0-7695-2235-1

Type

conf

DOI

10.1109/ATS.2004.16

Filename

1376554