DocumentCode :
2261822
Title :
Seed selection procedure for LFSR-based BIST with multiple scan chains and phase shifters
Author :
Arai, Masayuki ; Kurokawa, Harunobu ; Ichino, Kenichi ; Fukumoto, Satoshi ; Iwasaki, Kazuhiko
Author_Institution :
Graduate Sch. of Eng., Tokyo Metropolitan Univ., Japan
fYear :
2004
fDate :
15-17 Nov. 2004
Firstpage :
190
Lastpage :
195
Abstract :
In this paper, we discuss the application of a seed-selection procedure for LFSR-based BIST to multiple scan chains, combined with a phase shifter. We introduced the procedures for selecting seeds and arrangement of phase shifters under the restriction of limiting additional hardware overheads, and evaluated them in respect to the number of test patterns required to achieve 100% fault coverage. Experimental results shows that that the test length was reduced in comparison with cases in which phase shifters or seed-selection procedures were not applied, under condition where the number of EOR gates in the phase shifter were restricted.
Keywords :
VLSI; automatic test pattern generation; boundary scan testing; built-in self test; integrated circuit design; integrated circuit testing; logic design; shift registers; BIST; EOR gates; LFSR; multiple scan chains; phase shifters; seed selection procedure; test patterns; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Phase shifters; Semiconductor device testing; Test pattern generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2004. 13th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-2235-1
Type :
conf
DOI :
10.1109/ATS.2004.79
Filename :
1376557
Link To Document :
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