Hot Data-Aware FTL Based on Page-Level Address Mapping

The development of flash memory drives flash based SSD to enter into large-scale storage systems. The performance of SSD is highly dependent on the design of FTL. For the last few years, several FTL schemes have been proposed. Such as FAST, BAST, SAST etc. we design a novel FTL based on page-level mapping scheme. Since one of the major troubles of page-level mapping FTL is the unendurable memory consuming of the fine-grained mapping table. We propose a dedicated cache replacement policy called SRC to mitigate the memory pressure. Our FTL based on SRC is able to distinguish hot data from the cold. This capability highlights the garbage collection efficiency of page-level mapping schemes. As a result, the hot data-aware FTL reduces extra read/write operations by 10 times or more compared with FAST and BAST. As our FTL erases less blocks, the lifetime of SSD is extended by more than 30%. Further experiment shows that the hot data-aware FTL outperforms hybrid-level FTLs on workloads with varied read/write ratios.