Impact of process parameter variations on the energy dissipation in adiabatic logic

Adiabatic logic offers high energy savings compared to standard CMOS at moderate operating speeds. Until now, only rudimentary investigations of the robustness of adiabatic circuits were presented. However, in deep sub-micron technologies the deviation of the device parameters from their nominal value is of crucial importance. By means of Monte-Carlo simulations in a 130nm CMOS technology, the impact of the process parameter variations on the energy dissipation is derived, where both global and local variations are considered. Comparing the energy dissipation of the 97.7% percentiles of adiabatic families with the ones for static CMOS, energy savings up to a factor of 10 are observed.