A novel operational amplifier for low-voltage low-power SC circuits

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters to create the class-AB behavior in the first and second stages. With this structure, the transconductances (g_m) of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode Miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results present the sample-and-hold (S/H) of the 11-bit 40-MHz pipelined ADC using the proposed amplifier consumes only 5.5 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio(SNDR) 78.78 dB, spurious-free dynamic range (SFDR) 87.2 dB and total harmonic distortion (THD) -85.9 dB with 19.1 MHz full-swing input signal.