DocumentCode :
2262137
Title :
An integrated technique for test vector selection and test scheduling under test time constraint
Author :
Edbom, Stina ; Larsson, Erik
Author_Institution :
Dept. of Comput. Sci., Linkopings Univ., Sweden
fYear :
2004
fDate :
15-17 Nov. 2004
Firstpage :
254
Lastpage :
257
Abstract :
The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE´s (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the A TE memory depth.
Keywords :
automatic test equipment; electronic engineering computing; fault diagnosis; integrated circuit design; integrated circuit testing; integrated memory circuits; memory architecture; automatic test equipment; core-based designs; defect probability; fault coverage; faults detection; high test quality; test scheduling; test time constraint; test vector selection; Automatic test equipment; Automatic testing; Circuit faults; Circuit testing; Fault detection; Integrated circuit testing; Job shop scheduling; Processor scheduling; System testing; Time factors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2004. 13th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-2235-1
Type :
conf
DOI :
10.1109/ATS.2004.24
Filename :
1376567
Link To Document :
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