Title :
A Scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
Author :
Lin, Shu-Yen ; Hsu, Chan-Cheng ; Wu, An-Yeu Andy
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we proposed a scalable built-in self-test/self-diagnosis architecture, surrounding test ring (STR), to detect and locate faulty FIFOs and faulty MUXs for 2D-mesh based CMP systems. Proposed STR supports 97.79% fault coverage in FIFOs and MUXs and tests with 388 ~ 2886 test cycles in different testing methods and mesh sizes.
Keywords :
built-in self test; multiprocessing systems; 2D-mesh; FIFO; MUX; built-in self-test architecture; chip multiprocessor systems; self-diagnosis architecture; surrounding test ring; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Electric breakdown; Electronic equipment testing; Fault detection; Integrated circuit interconnections; Multiprocessing systems; System testing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118263
