DocumentCode
2262363
Title
A Improved Decoding Algorithm for Low-Density Parity-Check Codes
Author
Zhou, Wei ; Men, Ai-Dong ; Zhao, Li-Ye ; Quan, Zi-yi
Author_Institution
Sch. of Telecommun. Eng., Beijing Univ. of Posts & Telecommun., Beijing
fYear
2006
fDate
27-30 Nov. 2006
Firstpage
1
Lastpage
4
Abstract
Based on decoding performance, complexity and latency of finite-geometry low-density parity-check (LDPC) codes, an efficient decoding algorithm is proposed. The algorithm is a hybrid bit-flipping (BF)/majority-logic (MLG) algorithm. In the algorithm, there are two stages. At the first stage, a code is decoded with bit-flipping (BF) with a small fixed number of iterations. Then the output from bit-flipping (BF) decoder is decoded by majority-logic (MLG) decoding. And in bit-flipping (BF) decoding, a new method is used to find the least reliable position. In the hybrid algorithm, there aren´t real operations. Simulation results show that the algorithm provides 0.3dB coding gain over weight bit-flipping (WBF) decoding, and within 1 dB away from sum-product algorithm (SPA) decoding.
Keywords
decoding; majority logic; parity check codes; LDPC codes; decoding; hybrid bit-flipping algorithm; low-density parity-check codes; majority-logic algorithm; sum-product algorithm; weight bit-flipping decoding; Character generation; Delay; Encoding; Galois fields; Geometry; Iterative decoding; Linear feedback shift registers; Parity check codes; Shift registers; Sum product algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Technology, 2006. ICCT '06. International Conference on
Conference_Location
Guilin
Print_ISBN
1-4244-0800-8
Electronic_ISBN
1-4244-0801-6
Type
conf
DOI
10.1109/ICCT.2006.341793
Filename
4146394
Link To Document