A stochastic evolution based register allocation using multiport memories

In data path synthesis, intermediate outputs of functional blocks are stored in registers. Allocation of physical resources (register files) to registers is done by the designer. In some high level synthesis systems (CMU-DA), memory ports are allocated to registers with disjoint access times. In this paper, we present a stochastic evolution based approach to register allocation using multiport memories. In this approach allocation of registers to multiport memories proceeds in a way as to minimize the interconnection between memory ports and the functional units, while placing constraints on access time requirements of registers. This approach could be used in design space exploration to determine how many read/write ports per bank would best suit the application. We have implemented the algorithm and tested in on standard benchmarks. The approach yields good results