Title :
A novel approach for on-line testable reversible logic circuit design
Author :
Vasudevan, D.P. ; Lala, P.K. ; Parkerson, J.P.
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.
Keywords :
adders; circuit CAD; circuit complexity; design for testability; integrated circuit testing; logic gates; logic testing; MCNC benchmark circuits; carry-skip adders; circuit complexity; on-line testable reversible logic circuit design; online circuit testability; reversible digital circuits; testable reversible logic gates; testable ripple carry adders; Adders; Benchmark testing; Circuit testing; Computer science; Digital circuits; Energy dissipation; Logic circuits; Logic gates; Logic testing; Quantum computing;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Conference_Location :
Kenting, Taiwan
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.13
