Multimedia performance of a ubiquitous processor

The key to protect huge amount of multimedia data in ubiquitous networks is to introduce safety aware high-performed single VLSI processor systems embedded with cipher process. Thus, we exploited the architecture of a hardware cryptography-embedded multimedia mobile processor named HCgorilla by sophisticatedly unifying up-to-date processor techniques. Although it was provided with carefully selected Java byte codes and cipher codes, FP (floating point) expression was omitted due to the restriction of hardware resource. Considering recent trend of embedded applications like voice recognition, 3D graphics, and image/vision processing, FP hardware is crucial for further enhancing HCgorilla´s Java functions. We focus in this article the development of a compact FPU (Floating point number Processing Unit). A FP format specific for HCgorilla is IEEE 754 compatible except the bitwidth representation of FP data. Prioritizing the latency of FPU, it has only 5 stages, and it works at 400 MHz. FPU is built in HCgorilla by adding 16 FP arithmetic codes carefully selected from Java byte codes, and improving the decode stage of the previous HCgorilla. We have so far accomplished the logic synthesis and behavior simulation.