Title :
A high throughput deblocking filter design supporting multiple video coding standards
Author :
Chien, Cheng-An ; Chang, Hsiu-Cheng ; Guo, Jiun-In
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Abstract :
This paper presents a high throughput, VLSI architecture for multi-standard in-loop deblocking filter (ILF) supporting H.264 BP/MP/HP, AVS, and VC-1 video decoding. It comprises 38.4 Kgates and 672 bytes of local memory using TSMC 0.13 mum CMOS technology when operating at 225 MHz which meets the real-time processing requirement for high-resolution video decoding. We develop a PDB scheme and an integrated 1-D filter to realize various coding tools of the deblocking filter supporting multiple video coding standards.
Keywords :
CMOS integrated circuits; decoding; filtering theory; video coding; CMOS technology; PDB scheme; TSMC; VLSI architecture; frequency 225 MHz; high-resolution video decoding standard; multistandard in-loop deblocking filter; size 0.13 mum; throughput deblocking filter design; Adaptive filters; CMOS technology; Decoding; Information filtering; Information filters; MPEG 4 Standard; Optical filters; Quantization; Throughput; Video coding;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118278
