Analysis of fractional spur reduction using ΣΔ-noise cancellation in digital-PLL

In digital phase-locked loop based fractional-N RF frequency synthesizers, the use of a Time-to-digital converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of SigmaDelta-noise cancellation on the fractional spurs.