Title :
Reduce yield loss in delay defect detection in slack interval
Author :
Yan, Haihua ; Singh, Adit D.
Author_Institution :
Dept. of ECE, Auburn Univ., AL, USA
Abstract :
A new delay-testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. The simulation showed orders of magnitude delay defect detection efficiency improvement. In this paper we investigated the yield loss problem and proposed a practical production test based on delay defect detection in slack interval (DDSI).
Keywords :
delays; integrated circuit testing; integrated circuit yield; abnormal delays; delay defect detection; delay-testing scheme; slack interval; switching delays; yield loss reduction; Circuit faults; Circuit simulation; Circuit testing; Clocks; Delay effects; Electrical fault detection; Fault detection; Production; Switching circuits; Timing;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.74
