An all-digital phase-locked loop for digital power management integrated chips

An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-square, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-mum CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz.