Area efficient vector multiplication for IDDT test calibration

Author

Itskovich, M.

Author_Institution

Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland Baltimore County, Baltimore, MD, USA

fYear

2009

fDate

14-17 Sept. 2009

Firstpage

145

Lastpage

150

Abstract

This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the field programmable array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300 kHz, independently of vector size.

Keywords

encoding; field programmable gate arrays; integrated circuit testing; logic design; multiplying circuits; IDDT test calibration; binary encoded signal; field programmable array; signal processing architecture; vector multiplication; word length 8 bit; Calibration; Circuit testing; Computer science; Current measurement; Hardware; Impedance measurement; Probes; Semiconductor device measurement; Signal processing; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON, 2009 IEEE

Conference_Location

Anaheim, CA

ISSN

1088-7725

Print_ISBN

978-1-4244-4980-4

Electronic_ISBN

1088-7725

Type

conf

DOI

10.1109/AUTEST.2009.5314026

Filename

5314026

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2262798