LDPC decoder design for IEEE 802.15 standard

Author

Sha, Jin ; Lin, Jun ; Li, Li ; Minglun, Gao ; Wang, Zhongfeng

Author_Institution

Inst. of VLSI Design, Nanjing Univ., Nanjing, China

fYear

2009

fDate

24-27 May 2009

Firstpage

2441

Lastpage

2444

Abstract

This paper presents an efficient decoder design for the LDPC codes in IEEE 802.15 standard. This decoder features by high parallel level, low message memory requirement and code rate flexibility. By processing 72 columns and 72 rows in parallel, it can reach a throughput of 2.8 Gbps to fulfill the standard requirement. Furthermore, the decoder supports three different code rates by employing flexible check node processor units.

Keywords

decoding; parity check codes; personal area networks; IEEE 802.15 standard; LDPC decoder design; bit rate 2.8 Gbit/s; code rate flexibility; low density parity check code; message memory requirement; wireless personal area network; Block codes; Code standards; Digital video broadcasting; Iterative decoding; Parity check codes; Sections; Sparse matrices; Throughput; USA Councils; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118294

Filename

5118294

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2262807