Title :
A triple-mode LDPC decoder design for IEEE 802.11n SYSTEM
Author :
Chao, Min-An ; Wen, Jen-Yang ; Shih, Xin-Yu ; Wu, An-Yeu Andy
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the single-entry-multiple-data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n3). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13 mum CMOS, the proposed design is synthesized in 1.99 mm2 area at 172.4 MHz.
Keywords :
CMOS integrated circuits; codecs; parity check codes; wireless LAN; CMOS process; IEEE 802.11n; computational complexity; frequency 172.4 MHz; low density parity check codes; matrix reordering; single-entry-multiple-data scheme; size 0.13 mum; wireless LAN; Algorithm design and analysis; Bipartite graph; Decoding; Forward error correction; Hardware; MIMO; Parity check codes; Throughput; Very large scale integration; Wireless LAN;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118295
