A Reprogrammable and Scalable QoS Traffic Generator/Monitor on FPGA

Nowadays, high performance system/local area networks are filled by heterogeneous traffic, constituted by information flows with different bandwidth and latency requirements. The bottleneck existing between the network process elements speed (servers, routers,...) and the bandwidth in the links makes necessary new proposals in the design of these network components. The MMR (and its simplified version, the SMMR), a router which supports QoS, is a very well-known proposal in this area. In this article, we propose the architecture and implementation of a reprogramable and scalable traffic Generator/Monitor as support for the study, in a easy way, of this sort of routers. The Generator/Monitor is modular and has been implemented inside an FPGA using a high level hardware programming language such as the Handle-C. The result is a highly parameterizable platform, which allows prototyping the communication system of a high speed LAN/SAN environment, in order to study complexity reductions and optimizations of a router under different traffic conditions and server models.