Title :
A framework for testability metrics across hierarchical levels of assembly
Author :
Davidson, Scott ; Ungar, Louis Y.
Author_Institution :
Sun Microsyst., Inc., Sunnyvale, CA, USA
Abstract :
We cannot improve what we cannot measure and a major issue with system test today is that we do not know how effective it is in detecting defects, diagnosing failures, and ensuring field quality. This situation is in contrast to that of ICs, where test quality metrics have resulted in DPMs of 100 -1000 at board and system test and mean time to failures in the hundreds of millions of hours. This paper proposes a framework for system level coverage metrics, using fault sampling and a variety of defect models.
Keywords :
design for testability; failure analysis; fault location; integrated circuit testing; measurement standards; DFT; DPM; defect detection; failure analysis; fault coverage; fault sampling; testability metric framework; Assembly; Circuit faults; Circuit testing; Hardware; Integrated circuit modeling; Integrated circuit testing; Sampling methods; Sun; System testing; Telephony; DFT; fault coverage; testability;
Conference_Titel :
AUTOTESTCON, 2009 IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-4980-4
Electronic_ISBN :
1088-7725
DOI :
10.1109/AUTEST.2009.5314030
