Title :
Functional scan chain design at RTL for skewed-load delay fault testing
Author :
Ko, Ho F. ; Nicolici, Nicola
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
Abstract :
This paper introduces a new method to construct functional scan chains at the register-transfer level aimed at increasing the delay fault coverage when using the skewed-load test application strategy. It is shown how by consciously creating scan paths prior to logic synthesis, both the transition delay fault coverage and circuit speed can be improved.
Keywords :
design for testability; fault diagnosis; integrated circuit design; integrated logic circuits; RTL; circuit speed; functional scan chain design; high-level DFT; logic synthesis; register-transfer level; skewed-load delay fault testing; transition delay fault coverage; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Design for testability; Flip-flops; Logic circuits; Logic testing; Sequential analysis; Delay-fault testing; High-level DFT;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.47
