Floorplanning and thermal impact on leakage power and proper operation of complex SOC designs

In this paper, we demonstrate the need for considering the floorplan when the leakage power is calculated for a SoC. We proposed a leakage power estimation methodology which considers the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating leakage power. This methodology has been experimented with on three industrial SoC designs and we observed up to a 44.1% difference in leakage power between various floorplans. We believe that our estimation methodology is generic and can be useful for a wide variety of SoCs