Bus arbitration in an embedded processor-shared multiprocessor system

Author

Ramesh, Tirumale ; Ganesan, Subramaniam

Author_Institution

Dept. of Electr. Eng., Saginaw Valley State Univ., University Center, MI, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

320

Abstract

Bus arbitration scheme for a partially processor shared-memory system embedded in a general reconfigurable R(n,m) system is presented where n is the number of global processors, and m is the number of global memory modules. The effective cost for the arbitration and crosspoint switch control is absorbed within the hardware implementation of a SIMD array processor which can be used as a crosspoint switch controller. This embedded system shows an improvement of bandwidth over conventional group based bus systems

Keywords

computer networks; electronic switching systems; parallel architectures; real-time systems; reconfigurable architectures; system buses; SIMD array processor; bus arbitration scheme; crosspoint switch control; crosspoint switch controller; effective cost; embedded processor-shared multiprocessor system; embedded system; general reconfigurable system; global memory modules; global processors; group based bus systems; hardware implementation; partially processor shared-memory system; Bandwidth; Computer science; Costs; Embedded system; Fault tolerance; Hardware; Multiprocessing systems; Random access memory; Reconfigurable architectures; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343065

Filename

343065