Title :
A low-cost single-event latchup mitigation scheme
Author :
Nicolaidis, Michael
Author_Institution :
TIMA Lab., Grenoble
Abstract :
Single-event latchup is one of the most threatening single event effects as the induced current may destroy the affected device. Existing latchup mitigation schemes may induce a very high area cost or may require modifying the fabrication process. In this paper we present a new single-event latchup mitigation approach implemented at design level that protects devices from destruction and preserve circuit state at very low area cost
Keywords :
CMOS integrated circuits; integrated circuit design; radiation hardening (electronics); single-event effects; single-event latchup mitigation; Bipolar transistors; Circuit optimization; Costs; Error correction; Fabrication; Land surface temperature; Logic testing; Neutrons; Protection; Thyristors; Latchup; SEL; Single-event effects; lathcup; mitigation of single-event effects.; singleevent;
Conference_Titel :
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Conference_Location :
Lake Como
Print_ISBN :
0-7695-2620-9
DOI :
10.1109/IOLTS.2006.6
