DocumentCode
2263417
Title
A VLSI multistreaming RISC processor
Author
Choe, Swee-yew ; Chan, Choong-wah ; Chua, Hong-chuek
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fYear
1993
fDate
16-18 Aug 1993
Firstpage
296
Abstract
A multistreaming RISC processor for image processing implemented in VLSI is described. Multistreaming overcomes data and control dependencies inherent in pipeline execution. This approach is well suited for image processing where the availability of multiple independent tasks allows the pipeline to maintain its maximum throughput
Keywords
VLSI; digital signal processing chips; image processing; image processing equipment; pipeline processing; reduced instruction set computing; VLSI; image processing; maximum throughput; multiple independent tasks; multistreaming RISC processor; pipeline execution; Decoding; Hazards; Image processing; Pipelines; Read-write memory; Reduced instruction set computing; Registers; Streaming media; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location
Detroit, MI
Print_ISBN
0-7803-1760-2
Type
conf
DOI
10.1109/MWSCAS.1993.343071
Filename
343071
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