A single chip high-speed M-to-B arbiter for multiple bus multiprocessor systems

Author

Sheth, Devang G. ; Alles, Sheran ; Mahmud, Syed M.

Author_Institution

Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

284

Abstract

An M-user B-server synchronous arbitration circuit is built on a single chip using NMOS technology. The VLSI layout is modular which consists of 3 basic blocks: Type-1, Type-2, and Type-3. For VLSI layout of each block, one has to perform a few interconnections in order to build M-user B-server arbiter on a single chip. We have justified this statement by building arbiters for 16-user 4-server, 4-user 2-server, and 8-user 2-server. This arbiter design on a single chip can considerably reduce the space for total arbitration circuit in any multiprocessor system. At the same time it is faster and consumes less power

Keywords

MOS logic circuits; VLSI; asynchronous circuits; multiprocessing systems; sequential circuits; 16-user 4-server; 4-user 2-server; 8-user 2-server; M-user B-server synchronous arbitration circuit; NMOS technology; VLSI layout; high-speed M-to-B arbiter; multiple bus multiprocessor systems; total arbitration circuit; Binary trees; CMOS technology; Energy consumption; Hardware; Integrated circuit interconnections; Logic design; MOS devices; Multiprocessing systems; Space technology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343074

Filename

343074