Phase-locked loop automatic layout generation and transient fault injection analysis: a case study

This paper reports a case study about the automatic layout generation and transient fault injection analysis of a phase-locked loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. After layout validation, experiences were performed in the PLL in order to evaluate the sensibility against transient fault. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18mum). Results report the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults