FPGA acceleration of Sparse Matrix-Vector Multiplication based on Network-on-Chip

A new design concept for accelerating Sparse Matrix-Vector Multiplication (SMVM) in FPGA by using Network-on-Chip (NoC) is presented. In traditional circuit design on-chip communications have been designed with dedicated point-to-point interconnections or shared buses. Therefore, regular data transfer is the major concern of many parallel implementations. However, when dealing with the SMVM operation, which is the main step of most iterative algorithms for solving systems of linear equations, the required data transfers are usually dependent on the sparsity structure of the matrix and can be extremely irregular. Using a NoC architecture makes it possible to deal with arbitrary structure of the data transfers, i.e. with arbitrary structured sparse matrices. In this paper, a configurable interface is presented which can generate the pipelined SMVM calculator based on NoC architecture with size of 2×2, 4×4, ..., p×p (p ∈ ℕ). The implementation is done in IEEE-754 single floating-point precision on the Xilinx Virtex-6 FPGA.