FPGA implementation of a configurable viterbi decoder for software radio receiver

Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.