Title :
Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes
Author :
Rodríguez-Irago, M. ; Andina, J. J Rodríguez ; Vargas, F. ; Semiacy, J. ; Teixeira, I.C. ; Teixeira, J.P.
Author_Institution :
IST/INESC-ID Lisbon
Abstract :
Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations (DeltaVDD) and/or of temperature variations (DeltaT) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a DeltaVDDi or a DeltaTj variation. The on-chip availability of multiple VDD values in products with DVS (dynamic voltage scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained
Keywords :
built-in self test; digital systems; fault simulation; integrated circuit testing; BIST techniques; DVS; clock frequency; delay variation; digital systems; dynamic fault detection; dynamic voltage scaling; logic level; low-cost fault simulation; multitemperature schemes; nanometer products; on-chip availability; semiempirical analytical model; transient faults; variable power supply voltage; Analytical models; Built-in self-test; Clocks; Digital systems; Dynamic voltage scaling; Fault detection; Frequency; Power supplies; Temperature; Testing;
Conference_Titel :
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Conference_Location :
Lake Como
Print_ISBN :
0-7695-2620-9
DOI :
10.1109/IOLTS.2006.25
