Title :
A hardware cache coherency scheme for multiprocessors
Author :
Raja, Paruvachi V. ; Ganesan, Subramaniam
Author_Institution :
Oakland Univ., Rochester, MI, USA
Abstract :
In this paper, we discuss a hardware cache coherency scheme for shared memory multiprocessors. The scheme consists of a cache coherency protocol and a hardware scheme for cache coherency. Use of the scheme allows one to split cache coherency operations between the participating processors. Protocol states and operations are discussed. A cache controller architecture is proposed for this protocol and its design details are discussed. Performance of the coherency scheme is also discussed
Keywords :
cache storage; memory protocols; performance evaluation; shared memory systems; cache coherency protocol; cache controller architecture; hardware cache coherency scheme; protocol states; shared memory multiprocessors; Bandwidth; Broadcasting; Hardware; Memory architecture; Multiprocessing systems; Protocols; Watches;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343099
