Design and simulation of a 6th Order continuous-time sigma-delta modulator using integrated lc filter in a standard CMOS technology

A 6^th order bandpass continuous-time sigma delta modulator centered at 300MHz suitable for Software Defined Radio receiver is presented. This modulator is implemented in a standard low-cost 0.35μm CMOS technology. Several Q-enhanced LC resonators are implemented in a parallel structure using highly linear operational transconductance amplifiers (OTA), LC tank, and transconductor acts as a negative resistance to compensate the ohmic losses in inductor. Furthermore, an improved method employing two 3-bit flash ADC as a loop quantizer allows to double the sampling frequency and to relax the comparator requirements. Consequently we can design a modulator clocked at 1.2GHz allowing the integration of passive LC-filters in this standard technology. Transistor level simulations show that the modulator achieves a signal-to-noise and distortion-ratio (SNDR) of 82.6dB over a 6MHz signal band.