A cache coherency scheme for an asynchronous packet-switched shared memory multiprocessor

This paper analyses the problems encountered in designing a bus-based cache coherence protocol for an asynchronous packet switched multiprocessor system having private caches for each processor and describes such an implementation, showing the algorithm used in maintaining cache coherency. Multiple copies of the data are allowed to exist. Since there is no directory that keeps track of all the processors caching data, multiple messages need to be broadcast to all caches whenever coherency needs to be maintained. On the other hand, the scaleable coherent interface (SCI) protocol maintains a doubly linked-list of all caches sharing each data with the head pointer maintained at a memory controller. This paper will compare the above two schemes and discuss their corresponding performance and design issues for both small and large scaleable multiprocessors