Software-managed address translation

Author

Jacob, Bruce ; Mudge, Trevor

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

1997

fDate

1-5 Feb 1997

Firstpage

156

Lastpage

167

Abstract

In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that software-managed address translation is just as efficient as hardware-managed address translation and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms

Keywords

memory architecture; program interpreters; storage management; Mach; OSF/1; high clock-rate PowerPC implementation; memory management design; shared memory; software-managed address translation; sparse address spaces; sub-page protection; superpages; Clocks; Computer architecture; Energy management; Hardware; Jacobian matrices; Magnetic heads; Memory management; Operating systems; Power system management; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

High-Performance Computer Architecture, 1997., Third International Symposium on

Conference_Location

San Antonio, TX

Print_ISBN

0-8186-7764-3

Type

conf

DOI

10.1109/HPCA.1997.569652

Filename

569652