Title :
Efficient test circuit to qualify logic cells
Author :
Ribas, R.P. ; Bavaresco, S. ; Lubaszewski, M. ; Reis, A.I.
Author_Institution :
PGMicro - PPGC/UFRGS, Porto Alegre, Brazil
Abstract :
This work proposes a simple, efficient and easy-to-use test circuit for evaluating and validating any set of logic gates in terms of functionality, performance, power consumption and impact in operation of sub-nanometer physical effects.
Keywords :
logic design; logic gates; logic testing; logic cell; logic design; logic gates; power consumption; sub-nanometer physical effects; test circuit; Benchmark testing; Circuit testing; Delay; Energy consumption; Logic circuits; Logic design; Logic gates; Logic testing; Software libraries; Timing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118367
