Parallel and pipelined VLSI design for the histogramming operation

The authors describe the design of a VLSI processing unit for the histogramming operation. The processing unit is composed of several bit-serial processing elements (PEs) connected according to the odd-even network topology. In this approach, histogramming is divided into the counting process and the filtering process. The filtering process is shown to be computationally inexpensive compared to the counting and marking phases. The use of a histogramming unit of fixed size to handle a large number of pixels is considered