Novel, at-design-rule, via-to-metal overlay metrology for 193 nm lithography

Author

Ueno, Atsushi ; Tsujita, Katsuyoshi ; Kurita, Hiroshi ; Iwata, Yoshiyuki ; Adel, Merabet

Author_Institution

Process Dev. Dept., Renesas Technol. Corp., Hyogo, Japan

fYear

2003

fDate

30 Sept.-2 Oct. 2003

Firstpage

134

Lastpage

137

Abstract

The effect of scanner aberrations on the pattern placement errors (PPE) in the copper interconnect lithography process is studied both in simulations and experimentally. New grating-based AIM overlay mark enables measuring device feature overlay. It is shown that AIM mark exhibits superior performance over conventional box-in-box (BiB) marks. Comparison between Archer AIM optical and direct CD SEM device overlay measurements was done. Both CD SEM and AIM optical measurements show sensitivity to PPE. Good matching between AIM and device overlays was demonstrated.

Keywords

aberrations; error analysis; integrated circuit interconnections; integrated circuit manufacture; integrated circuit measurement; integrated circuit modelling; lithography; scanning electron microscopy; sensitivity; spatial variables measurement; 193 nm; Archer AIM optical device; Cu; conventional box-in-box marks; design-rule; device feature; direct CD SEM device overlay; interconnect lithography process; metal overlay metrology; pattern placement errors; scanner aberrations; Gratings; Lenses; Lighting; Lithography; Metrology; Nonlinear optics; Optical interconnections; Optical sensors; Predictive models; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2003 IEEE International Symposium on

ISSN

1523-553X

Print_ISBN

0-7803-7894-6

Type

conf

DOI

10.1109/ISSM.2003.1243249

Filename

1243249