Use of ADC/RTC to trace intermittent and rare events causing yield limiting front-end defects in deep sub-micron CMOS processes

Author

Leroux, Paul ; Singh, Karam ; Pierce, Brennand ; Luna, E.

fYear

2003

fDate

30 Sept.-2 Oct. 2003

Firstpage

165

Lastpage

168

Abstract

The ability to detect yield-limiting defects during processing reduces the number of learning cycles needed to solve problems. Traditional inspection equipment provide a distribution over a wide range of defect types. ADC (Automatic Defect Classification) and RTC (Real Time Classification) on bright field inspection tools help provide insight into the distribution of on-wafer defect types. In our particular case, ADC was used to track the severity of a yield limiting front-end defect on our 0.25 μm process line. Most semiconductor factories will trend random defects or added defects in their SPC system, but few have the capability to trend a specific defect type at an inspection point.

Keywords

CMOS integrated circuits; electronics industry; failure analysis; integrated circuit reliability; integrated circuit yield; semiconductor device manufacture; semiconductor technology; tracers; 0.25 micron; automatic defect classification; deep submicron CMOS processes; field inspection tools; learning cycles; on-wafer defect; random defects; real time classification; semiconductor factories; yield limiting front-end defects; CMOS process; Condition monitoring; Event detection; Failure analysis; Inspection; Problem-solving; Random access memory; Testing; USA Councils; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2003 IEEE International Symposium on

ISSN

1523-553X

Print_ISBN

0-7803-7894-6

Type

conf

DOI

10.1109/ISSM.2003.1243256

Filename

1243256