Title :
Systolic implementation of FIR decimators and interpolators
Author :
Abdel-Raheem, E. ; El-Guibaly, F. ; Antoniou, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
Efficient VLSI systolic implementations of FIR decimators and interpolators are obtained by mapping their difference equations using an algebraic approach. The structures obtained are modular and pipelined. Pipelining can be introduced at the input, the output or both and results in several structures. Each processing element consists of a single multiplier and storage requirements depend on the decimator or interpolator factor. The number of multipliers is reduced in proportion to the decimation or interpolation factor
Keywords :
FIR filters; VLSI; difference equations; digital filters; interpolation; pipeline processing; systolic arrays; FIR decimators; FIR interpolators; VLSI; decimation factor; difference equations; interpolation factor; multiplier; pipelining; processing element; systolic implementation; Difference equations; Digital filters; Filtering; Finite impulse response filter; High performance computing; IIR filters; Interpolation; Pipeline processing; Sampling methods; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343223
