High-performance designs of AES transformations

Both area and throughput are significant for hardware implementations of the Advanced Encryption Standard (AES). Previous works mostly focused on area without providing full control on critical path delay (CPD), which ultimately determines throughput. To address this issue, we propose a delay-aware common subexpression elimination (DACSE) algorithm that is novel in two aspects: it not only takes advantage of implicit common subexpressions to further reduce area, but also minimizes area while satisfying any feasible CPD requirement. Using our DACSE algorithm, we propose high-performance designs for two major transformations of the AES, MixColumns and SubBytes. Compared with prior works, our designs achieve the same or shorter CPDs with the same or smaller gate counts.