Transistor sensitivity to energy contamination from decelerated BF2 and As ion implantation

Decel mode implantation provides a significant increase in beam current at low implant energies. In this work, we investigate decel-induced energy contamination in NMOS and PMOS source/drain (S/D) extension implants. Drift mode, decel mode, and dual-energy drift mode implants are used to obtain transistor parametric sensitivity to the dose of energy contamination. In addition, we characterize implant-to-implant repeatability of energy contamination. The results are used to estimate the effect on transistor parametric variation in a manufacturing environment.