DocumentCode
2265470
Title
Integrated yield enhancement strategy for advanced 130 nm BEOL copper process
Author
Zhang, Juyong
fYear
2003
fDate
30 Sept.-2 Oct. 2003
Firstpage
243
Lastpage
246
Abstract
This paper presents an integrated yield enhancement strategy which utilizes a combination of SRAM bitmap and other techniques to achieve fast yield learning for advanced 130 nm copper process. As device manufacturers implement copper manufacturing capability at increasing smaller geometries, it is crucial to detect, understand and eliminate copper process induced defects. Defect modes from copper dual-damascene process are different from those in the subtractive Aluminium process. At 130 nm node, buried defects and poor interface issues are examples of yield destroying defects that are difficult to detect by conventional inline scan. SRAM-based bitmap proved to be crucial to unveil these defects using focus-ion beam (FIB) to obtain precise cross-sectional view of the failed bits.
Keywords
SRAM chips; aluminium; copper; focused ion beam technology; integrated circuit metallisation; integrated circuit testing; integrated circuit yield; 130 nm; Al; Cu; FIB; SRAM bitmap; back end line copper process; copper dual-damascene process; copper manufacturing capability; copper process induced defects; device manufacturers; focus-ion beam; integrated yield enhancement strategy; subtractive aluminium; yield analysis; yield destroying defects; Aluminum; Copper; Geometry; Integrated circuit interconnections; Logic; Manufacturing processes; Monitoring; Random access memory; Semiconductor device manufacture; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2003 IEEE International Symposium on
ISSN
1523-553X
Print_ISBN
0-7803-7894-6
Type
conf
DOI
10.1109/ISSM.2003.1243274
Filename
1243274
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