Integrated electrical and SEM defect characterization for rapid yield ramp

With the increasing cost of advanced semiconductor fabs, the economic motivations for an accelerated, efficient yield ramp are greater than ever. However the technical difficulties with increasing process complexity, shrinking design rules and new materials are extremely challenging. Complex interactions between process and product layout produce a wide array of systematic and optically invisible defect mechanisms, which account for an ever-increasing part of the yield loss. Therefore, it becomes important so that the speedy analytic tool which specifies a defective factor precisely may carry out rapid yield rate improvement. This paper describes a powerful new approach to inline defect characterization enabling systematic and random defect metrology that uses BEOL test structures to model design specific process dependencies. The process includes an efficient defect analysis flow including automated data analysis, inline electrical testing and Automatic Defect Localization of optically invisible defects on a SEM review tool. This allows the generation of a comprehensive report of main systematic and random failure mechanisms. In this paper we describe the methodology implemented at SCE ´s 90 nm Cu development line in Nagasaki, Japan.