A new approach for the design of CMOS voltage buffers for switched-capacitor and gm-C filters

Author

Barúqui, Fernando A P ; Petraglia, Antonio

Author_Institution

COPPE, Fed. Univ. of Rio de Janeiro, Rio de Janeiro, Brazil

fYear

2009

fDate

24-27 May 2009

Firstpage

2970

Lastpage

2973

Abstract

Buffers are widely employed as basic building blocks in time delay lines and in interfacing integrated circuits with the external world. This paper presents a new CMOS analog fully differential voltage buffer developed for minimum power consumption, large dynamic range and low harmonic distortion. Its design is based on the use of cross-coupled input differential pairs and internal current feedback. Two design approaches are proposed: one for switched-capacitor circuits and the other for gm-C circuits. Illustrative design examples are developed for a 0.35 - "m"m CMOS technology using a power supply voltage of 2.5 V. Spice simulations using BSIM3 device models are shown to support the theory.

Keywords

CMOS analogue integrated circuits; harmonic distortion; network synthesis; switched capacitor filters; CMOS analog circuits; CMOS technology; CMOS voltage buffers; harmonic distortion; power consumption; power supply voltage; switched-capacitor; time delay lines; voltage 2.5 V; CMOS technology; Delay effects; Dynamic range; Energy consumption; Feedback; Harmonic distortion; Power harmonic filters; Power supplies; Switched capacitor circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118426

Filename

5118426