A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments

Due to the rising importance of virtualization, extensive efforts have gone into determining and improving the performance of workloads on virtualized platforms. This has resulted in a series of modifications to the leading architecture used in virtualized system (x86) by adding hardware support for virtualization, the latest of which is the addition of tags and tag comparators to the x86 TLB. In this context, it is necessary to have a thorough understanding of the TLB behavior of virtualized workloads and understand the change in this behavior with TLB related architectural parameters. One way of obtaining this understanding is by conducting a simulation-based study of the interaction of various micro-architectural parameters and their effect on the TLB behavior. However, the lack of suitable simulation frameworks makes such a study daunting. In this paper, we present a full-system simulation framework which is suitable for conducting such studies. We first motivate the need for TLB modeling in virtualized systems. Then, we present the framework, develop and validate a timing model for the TLB and evaluate the simulation speed when this model is used. Using the timing model, the influence of the TLB on workload performance is examined for a variety of single and multi-domain workloads and compared with equivalent non-virtualized workloads. It is found that the performance of virtualized workloads, in terms of instructions per cycle (IPC), can vary by 1% to 35% due to the TLB and that this IPC variation can be as much as 9 times the variation in non-virtualized workloads.