An effective method of characterization poly gate CD variation and its impact on product performance and yield

Author

Xiao-Yu Li ; Feng Wang ; Wang, Michael ; Horng Nan Chern

Author_Institution

Xilinx, San Jose, CA, USA

fYear

2003

fDate

30 Sept.-2 Oct. 2003

Firstpage

259

Lastpage

262

Abstract

Poly gate CD variation has been increasingly affecting product performance and yield in advanced process technology. Here a BIST pattern based poly gate CD measurement (tilo) methodology is introduced in FPGA product. FPGA circuit is programmed into small local BIST pattern (tilo) and its delay is accurately reflecting local poly gate CD and variation. This methodology can conveniently capture poly gate CD statistical variation at both intra field and inter field level. The paper shows that this tilo measurement is very useful in guiding poly process debugging and yield improvement work.

Keywords

built-in self test; delay circuits; elemental semiconductors; field programmable gate arrays; integrated circuit measurement; integrated circuit yield; silicon; statistical analysis; BIST pattern; FPGA circuit; Si; delay; intra field level; methodology; poly gate CD measurement; poly gate CD statistical variation; poly process debugging; product performance; yield improvement; yield process technology; Built-in self-test; Delay; Electric variables measurement; Field programmable gate arrays; Integrated circuit interconnections; Lenses; Programmable logic arrays; Random access memory; Ring oscillators; Scanning electron microscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2003 IEEE International Symposium on

ISSN

1523-553X

Print_ISBN

0-7803-7894-6

Type

conf

DOI

10.1109/ISSM.2003.1243278

Filename

1243278