Characteristics of complementary noise immune logic (CNIL) in a high speed ECL technology

Author

Hendrickson, Thomas E. ; Machacek, Dave

Author_Institution

Dept. of Electr. Eng., Mankato State Univ., MN, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

1037

Abstract

Recently a new type of high performance logic was reported by R.J. Gravrok and R.M. Warner (1987). Dubbed Complementary Noise Immune Logic (CNIL), this family was designed to yield high noise immunity while supporting large fan-outs and fan-ins at moderate power and high speed. Although the authors reported on the basic concepts and design style of this logic form, their report failed to provide specific, comparative results for CNIL implemented in a modern, high speed process. In this paper we report on our initial work in this area. Simulation results are given and discussed for speed variations with fan-out, power, and temperature. Key elements of the switching delay are identified and potential improvements are suggested and analyzed

Keywords

bipolar logic circuits; circuit analysis computing; delays; emitter-coupled logic; integrated circuit noise; complementary noise immune logic; high noise immunity; high speed ECL technology; large fan-ins; large fan-outs; speed variations; switching delay; Circuit simulation; Computational modeling; Delay; Logic arrays; Logic circuits; Logic design; Logic devices; Semiconductor device noise; Semiconductor diodes; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343248

Filename

343248