Analysis and design of memoryless interconnect encoding scheme

Author

Chen, Ge ; Duvall, Steven ; Nooshabadi, Saeid

Author_Institution

Sch. of Electr. Eng. & Telecommun., Univ. of New South Wales, Sydney, NSW, Australia

fYear

2009

fDate

24-27 May 2009

Firstpage

2990

Lastpage

2993

Abstract

Coupling capacitance between adjacent wires in on-chip busses significantly increases the average transition energy dissipation. This paper develops a mathematical model for a memoryless encoding scheme and proposes a novel partitioning method for reducing the transition energy. Specifically, for an 8-bit bus in 65 nm CMOS technology, we present an 11-wire solution that reduces energy dissipation by 22%. The proposed scheme achieves similar energy efficiency without increasing the complexity of the encoding and decoding circuitry when the bus is extended to 16, 32 and 64 bits.

Keywords

CMOS integrated circuits; CMOS logic circuits; combinational circuits; decoding; integrated circuit design; integrated circuit interconnections; memoryless systems; CMOS technology; combinational logic circuit; coupling capacitance; decoding circuitry; mathematical model; memoryless interconnect encoding scheme; on-chip bus; partitioning method; size 65 nm; CMOS technology; Decoding; Encoding; Energy consumption; Energy dissipation; Integrated circuit interconnections; Mathematical model; Parasitic capacitance; Voltage; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118431

Filename

5118431