A high speed and low power on CMOS/SOI technology and its modelings

Reduction of parasitic capacitances has predicted two-time high speed in deep-submicron CMOS/SIMOX ring oscillators (RO), where measurements are plotted for comparison with an analytical model with ultra-thin SOI film thickness of 30-nm and 50-nm. Analytical lower bounds for power dissipations of a CMOS/SOI inverter using a time-dependent capacitance model and the conventional model are propounded. It is concluded that (1) noticable results show high speed (24 ps/stage at the gate length of 0.15-μm and supply voltage of 2.0 V) at 50-nm SOI-film thick and very low power (6 μW/stage at the gate length, L_g, of 0.2-μm and supply voltage, V_dd, of 1.5 V) at 30-nm SOI-film thick CMOS/SOI ring oscillator, while models at 30-nm SOI-film as poly-Si gate thickness decreases predicted comparable high speed (24 ps/stage at L_g=0.1-μm with V_dd=2.5 V) like 50-nm SOI-film devices. This is promising for high performance of deep-submicron gate ultra-thin film CMOS/SOI technology at low voltage operations